I have not yet managed to have the Q&A lecture of 25-May appear in the schedule, so I add a link here for you to access the podcast.

May 25, 2020 1:32 PM

Dear students,

due to the Corona crisis the written exam cannot be held in one room as planned. The faculty of mathematics and natural science has thus decreed that most written exams will be remodelled to be home exams and that the final mark willl be pass/fail. The home exams shall require about a two days work effort and a 7 days deadline to complete, starting from the original exam date. For IN3170/IN4170 the home exam shall take the form of a Cadence schematics design task, probably suplemented with a few theoretical questions. The design task will be somewhat more 'creative' than lab 3: you will be given some performance specifications and will have to design a small circuit that comes as close as possible to fullfilling these specifications.

Apr. 6, 2020 11:05 AM

Dear students,

 

a new version of lab 3 has just been uploaded. Some blanks have been filled in with respect to the correct Cadence library names and cell names of transistors to be used in 65nm technology.

Mar. 19, 2020 2:51 PM