IN5050 – Programming Heterogeneous Multi-Core Architectures
The course addresses issues related to heterogeneous multi-core architectures that are today found in all computing devices ranging from mobile phones, commodity desktops to large computing clusters.
The students will learn how asymmetric cores, threading models, memory hierarchies and interconnect technologies determine whether decisions that are made in the parallel implementations of example algorithms are successful or not.
The students will get hands-on experience of this challenge by programming three different architectures. During the course, the students will understand the challenges in writing efficient programs for the different architectures. Programming and documenting the effect of alternative choices are an important part of the course.
The three concrete architectures change with the current relevance for the market. Currently, students will experience dedicated SIMD units in low-power CPUs (ARM), graphics processing units (GPUs, NVidia) and machines interconnected by PCI Express interconnect (Dolphin ICS).
After completing the course you:
- have an understanding of the ties between good parallelization choice and concrete parallel architectures and parallelization frameworks (e.g. threading, vectorization, and combinations).
- are knowledgeable about different ways of solving parallelization tasks for alternative parallelization models, memory hierarchies and system architectures.
- have a good insight into the evaluation of alternative design and implementation options for parallelization depending on an architecture and framework.
- are knowledgeable about locating, understanding and fixing bottlenecks in parallel programs
- have an understanding of typical pipelines for multimedia workloads such as video encoders
- know the architecture and framework of three widely used contemporary platforms for parallel programming
- can program and profile three widely-used platforms
- have experience in presenting an assessment of alternative problem solutions in oral, written and poster formats
Students admitted at UiO must apply for courses in Studentweb. Students enrolled in other Master's Degree Programmes can, on application, be admitted to the course if this is cleared by their own study programme.
Nordic citizens and applicants residing in the Nordic countries may apply to take this course as a single course student.
If you are not already enrolled as a student at UiO, please see our information about admission requirements and procedures for international applicants.
Recommended previous knowledge
- 10 credits overlap with IN9050 – Programming Heterogeneous Multi-Core Architectures
- 10 credits overlap with INF5063 – Programming heterogeneous multi-core architectures (continued)
- 10 credits overlap with INF9063 – Programming heterogeneous multi-core architectures (continued)
- 5 credits overlap with INF5062 – Programming asymmetric multi-core processors (discontinued)
The course will consist of
- Lectures: 24 hours (in sets of 4 hours)
- Attendance is not mandatory
- Group lectures: 12 hours (in sets of 3 blocks)
- Attendance is not mandatory
- Three oral, interactive poster presentations: 9 hours (in sets of 3 hours)
- Presentation is mandatory
- Attendance of all presentations is mandatory
- Only valid in the same semester
- Three home exams
- Report about platform-specific choices and performance achievements (graded)
- Working source code (graded)
- Poster illustrating performance results (mandatory but not graded)
Three graded home exams, each consisting of source code and a report.
- Each home exam has approximately equal weight (~33%)
- Missing home exams without valid reasons count as an F
All parts of the exam must be passed, and in the same semester.
Examination support material
All, but no text or code must be copied verbatim from other sources.
Language of examination
You may write your examination paper in Norwegian, Swedish, Danish or English.
Grades are awarded on a scale from A to F, where A is the best grade and F is a fail. Read more about the grading system.
Explanations and appeals
Resit an examination
This course offers both postponed and resit of examination. Read more:
Withdrawal from an examination
It is possible to take the exam up to 3 times. If you withdraw from the exam after the deadline or during the exam, this will be counted as an examination attempt.
It will also be counted as one of your three attempts to sit the exam for this course, if you sit the exam for one of the following courses: IN9050 – Programming Heterogeneous Multi-Core Architectures, INF5063 – Programming heterogeneous multi-core architectures (continued), INF9063 – Programming heterogeneous multi-core architectures (continued)
Special examination arrangements
Application form, deadline and requirements for special examination arrangements.