Chapter 10 (Except: 10.5 and 10.6)
Chapter 11 (Except: 11.3, 11.4, 11.5 and 11.6)
Chapter 14 (Except: 14.3, 14.5 and 14.9)
Chapter 15 (Except: 15.4)
Chapter 16 (Except: 16.3 and 16.4)
Chapter 17 (Except: 17.4.2, 17.4.3, 17.4.4, 17.6.1 and 17.8)
Chapter 18 (Except: 18.2.6, 18.2.7, 18.6, 18.8 and 18.9)
Chapter 19 (Except: 19.3, 19.4.3 and 19.5)
The final report should be submitted through Devilry. If you have problems, send the report on email to Girish, Rikesh and me within tomorrow at 23.59.
Since most students seem to need a couple of more days to complete, we can extend the deadline until May 11th. That is a hard deadline since we need to assess the reports and notify the administration two weeks before the exam.
Tohid's presentation on Integrating ADC can be found here Control_logic_ppt.pdf
Rikesh and Girish have made a possible control logic implementation for the project. It may be found here: control_logic---test_dac.zip
Since the ADC chapter is not reached before next week, the first deadline in the design project is extended until 13.03.2017.
To get more background on the project, the relevant data converter chapters (15 and 17) will be lectured earlier than originally planned. Chapter 13 and 14 will be postponed two weeks.
Previous exams can be found here:
The course design project will be presented Monday January 30th. Groups of two students will be set up. Feel free to form groups in advance.