Teaching plan

Date Teacher Place Topic Lecture notes / comments
13.01.2014 Jørgen Norendal and Roar Skogstrøm. Postscript

INF5430 course presentation.

Digital HW design 1. Sequential circuit design and Register Transfer Methodology: Principle

P.P. Chu chapter 9.1-3 and 9.5. Slides
16.01.2014 Roar Skogstrøm Perl Digital Arithmetic HW Design 1 Israel Koren: Computer Arithmetic Algorithms. Lecture slides
20.01.2014 Jørgen Norendal Postscript Digital HW design 2. Register Transfer Methodology: Principle P.P.Chu chapter 11 and 12.1-5.Slides
23.01.2014 Jørgen Norendal  Perl Digital HW design 3. Clock and synchronization. P.P.Chu chapter 16.5-11. Slides
27.01.2014 Roar Skogstrøm Postscript Digital Arithmetic HW Design 2 Israel Koren: Computer Arithmetic Algorithms.  Lecture slides

Roar Skogstrøm,

Dag Halfdan Bryn

Perl Digital Arithmetic HW Design 3 + Intro. to lab1 Israel Koren: Computer Arithmetic Algorithms Lecture slides, and lab1 Introduction to MIPS processor and digital arithmetic.
03.02.2014 Roar Skogstrøm Postscript Digital Arithmetic HW Design 4 + SystemVerilog 1 Integer division arithmetic Lecture slides .
06.02.2014 Alexander Wold Perl Partial Reconfiguration 1 The lecture slides are here .
10.02.2014       CANCELLED
13.02.2014 Alexander Wold Perl Partial Reconfiguration 2  
17.02.2014 Roar Skogstrøm Postscript SystemVerilog 1 Introduction to SystemVerilog and SystemVerilog for Verification chapter 1 Lecture slides. SystemVerilog for design reference books are here . Complete solutions to all end of chapter exercises in the book are here .
20.02.2014 Roar Skogstrøm Perl SystemVerilog 2 SystemVerilog for Verification chapter 2 Lecture slides.
24.02.2014 Espen Tallaksen Postscript VHDL Testbench Design 1 Making good testbenches with Bitvis Utility Library; Lecture slides  (www.bitvis.no).
27.02.2014 Roar Skogstrøm Perl DesignSystemVerilog 3 SystemVerilog for Verification chapter 3 Lecture slides.
03.03.2014 Roar Skogstrøm Postscript VHDL Testbench Design 2 Command driven VHDL testbenches  Lecture slides . P.J.Ashenden: The Designers Guide to VHDL; Chapter 17 (17.1-2). A complete example of a command driven testbench is here and with slides here. This example is NOT part of the curriculum.
06.03.2014 Roar Skogstrøm Perl SystemVerilog 4 SystemVerilog for Verification chapter 4  Lecture slides.
10.03.2014 Jørgen Norendal Postscript Low Power HW Design 1 Jan Rabaey: Low Power Design Essentials chapter 1, 3, 4 and 5. Lecture slides
13.03.2014 Roar Skogstrøm Perl SystemVerilog 5 SystemVerilog for Verification chapter 5 Lecture slides .
17.03.2014 Jørgen Norendal Postscript Low Power HW Design Jan Rabaey: Low Power Design Essentials chapter 6, 8, 10 and 12. Lecture slides and article from EETimes
20.03.2014 Roar Skogstrøm Perl SystemVerilog 6

SystemVerilog for Verification chapter 7 Lecture slides.

24.03.2014 Roar Skogstrøm Postscript SystemVerilog 7

Some SystemVerilog questions and answers are here . SystemVerilog for Verification chapter 8 and 10 Lecture slides.

27.03.2014 Roar Skogstrøm Perl SystemVerilog 8 SystemVerilog for Verification chapter 6  Lecture slides.  Write-Only-Memory (WOM) datasheet (joke!!).
31.03.2014 Alexander Wold Postscript High Level Synthesis The lecture slides are here .
03.04.2014       CANCELLED
07.04.2014 Roar Skogstrøm Postscript SystemVerilog 9 SystemVerilog for Verification chapter 9 Lecture slides.
10.04.2014 Roar Skogstrøm Perl SystemVerilog Universal Verification Methodology (UVM) SystemVerilog UVM slides and MPEG4 files are here (304 MByte!)


Published Jan. 9, 2014 12:06 PM - Last modified Apr. 8, 2014 8:13 PM