IN9050 – Programming heterogeneous multi-core architectures
Changes in the course due to coronavirus
Autumn 2020 we plan for teaching and examinations to be conducted as described in the course description and on semester pages. However, changes may occur due to the corona situation. You will receive notifications about any changes at the semester page and/or in Canvas.
Spring 2020: Teaching and examinations was digitilized. See changes and common guidelines for exams at the MN faculty spring 2020.
The course addresses issues related to heterogeneous multi-core architectures that are today found in all computing devices ranging from mobile phones, commodity desktops to large computing clusters.
The students will learn how asymmetric cores, threading models, memory hierarchies and interconnect technologies determine whether decisions that are made in the parallel implementations of example algorithms are successful or not.
The students will get hands-on experience of this challenge by programming three different architectures. During the course, the students will understand the challenges in writing efficient programs for the different architectures. Programming and documenting the effect of alternative choices are an important part of the course.
The three concrete architectures change with the current relevance for the market. Currently, students will experience dedicated SIMD units in low-power CPUs (ARM), graphics processing units (GPUs, NVidia) and machines interconnected by PCI Express interconnect (Dolphin ICS).
After finishing the course you´ll
- have an understanding of the ties between good parallelization choice and concrete parallel architectures and parallelization frameworks (e.g. threading, vectorization, and combinations).
- are knowledgeable about different ways of solving parallelization tasks for alternative parallelization models, memory hierarchies and system architectures.
- have a good insight into the evaluation of alternative design and implementation options for parallelization depending on an architecture and framework.
- are knowledgeable about locating, understanding and fixing bottlenecks in parallel programs
- have an understanding of typical pipelines for multimedia workloads such as video encoders
- know the architecture and framework of three widely used contemporary platforms for parallel programming
- have experience in presenting an assessment of alternative problem solutions in oral, written and poster formats
- have insight into the state-of-the-art in parallelization for a selected platform
- have experience in parallelizing a real-world workload
- have experience in presenting a lecture to master-level students
Admission to the course
PhD candidates from the University of Oslo should apply for classes and register for examinations through Studentweb.
If a course has limited intake capacity, priority will be given to PhD candidates who follow an individual education plan where this particular course is included. Some national researchers’ schools may have specific rules for ranking applicants for courses with limited intake capacity.
PhD candidates who have been admitted to another higher education institution must apply for a position as a visiting student within a given deadline.
Recommended previous knowledge
- 10 credits overlap with IN5050 – Programming Heterogeneous Multi-Core Architectures.
- 10 credits overlap with INF5063 – Programming heterogeneous multi-core architectures (continued).
- 10 credits overlap with INF9063 – Programming heterogeneous multi-core architectures (continued).
- 5 credits overlap with INF5062 – Programming asymmetric multi-core processors (discontinued).
The course will consist of
- Lectures: 24 hours (currently in 4 blocks)
- Attendance is not mandatory
- Group lectures: 12 hours (in 4 blocks)
- Attendance is not mandatory
- Three oral, interactive poster presentations: 9 hours (in 3 blocks)
- Presentation of extensive project’s progress is mandatory
- Attendance of all presentations is mandatory
- Only valid in the same semester
- One home exam
- Report about background of the extensive real-world application that is the subject of parallelization, related work, platform-specific choices, and performance assessment (pass/fail)
- Working source code (pass/fail)
- Poster illustrating performance results (mandatory but not graded)
- A 30-minute lecture about a particular real-world test case
One graded home exam consisting of source code, a report, and a presentation in lecture style.
All parts of the exam must be passed, and in the same semester.
It will also be counted as one of your three attempts to sit the exam for this course, if you sit the exam for one of the following courses: IN5050 - Programming Heterogeneous Multi-Core Architectures, INF5063 - Programming heterogeneous multi-core architectures (continued), INF9063 - Programming heterogeneous multi-core architectures (continued)
Examination support material
All, but no text or code must be copied verbatim from other sources.
Grades are awarded on a pass/fail scale. Read more about the grading system.
Resit an examination
Students who can document a valid reason for absence from the regular examination are offered a postponed examination at the beginning of the next semester. Re-scheduled examinations are not offered to students who withdraw during, or did not pass the original examination.